With increasing development of semiconductor technology, and with downsizing of process nodes, the gate-last technology has been widely used to achieve desired threshold voltage and to improve device performance. However, when critical dimensions of devices further decrease, even if the gate-last technology is used, conventional MOS field effect transistors (FETs) are not able to meet the requirements on the device performance. Thus, multi-gate devices have been widely used.
Fin field effect transistors (Fin FETs) are multi-gate devices which are widely used nowadays. FIG. 1 is a perspective view of a common type of Fin FET. As shown in FIG. 1, the Fin FET includes a substrate 10 and a fin structure 14 protruding from the substrate 10. A dielectric layer 11 is disposed to cover the substrate 10 on opposite sides of the fin structure 14 and to cover a portion of sidewalls of the fin structure 14. A gate structure 12, including a gate dielectric layer and a gate electrode layer (not shown in FIG. 1), is disposed on the dielectric layer 11. The gate structure 12 stretches over the fin structure 14, partially covering the top surface and sidewalls of the fin structure 14. A source region and a drain region are respectively disposed within the fin structure 14 on both sides of gate structure 12. On the top surface and sidewalls of the fin structure 14, several regions are in contact with the gate structure 12. Therefore, multiple channel regions are formed, which may increase the drive current of the Fin FET and improve the device performance. However, when process nodes shrink further, problems may occur and affect performance of the Fin FET device.
Therefore, there is a need to provide a Fin FET and a method for forming the Fin FET with improved device performance